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dsp56f802/d rev. 0 , 1/2002 ? motorola, inc., 2002. all rights reserved. dsp56f80 2 preliminary technical data dsp56f802 16-bit digital signal processor ? up to 40 mips operation at 80 mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ?8k 16-bit words program flash ?1k 16-bit words program ram ?2k 16-bit words data flash ?1k 16-bit words data ram ?2k 16-bit words boot flash ? hardware do and rep loops ? 6-channel pwm module with fault input ? two 12-bit adcs (1 x 2 channel, 1 x 3 channel) ? serial communications interface (sci) ? two general purpose quad timers with 2 external outputs ?jtag/once tm port for debugging ? 4 shared gpio ? on-chip relaxation oscillator ? 32-pin lqfp package figure 1. dsp56f802 block diagram jtag/ once port digital reg analog reg low voltage supervisor program controller and hardware looping unit data alu 16 x 16 + 36 ? 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit 16-bit dsp56800 core pab pdb xdb2 cgdb xab1 xab2 interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset reset application- specific memory & peripherals interrupt controller program memory 8188 x 16 flash 1024 x 16 sram boot flash 2048x 16 flash data memory 2048 x 16 flash 1024 x 16 sram cop/ watchdog sci0 or gpio quad timer d or gpio quad timer c a/d1 a/d2 adc 2 2 3 2 6 pwm outputs pwma 16 16 vcapc v dd v ss *v dda v ssa 5 22 3 vref pll relaxation oscillator . * includes tcs pin which is reserved for factory use and is tied to vss fault a0
2 dsp56f802 preliminary technical data motorola part 1 overview 1.1 dsp56f802 features 1.1.1 digital signal processing core ? efficient 16-bit dsp56800 family dsp engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80 mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators including extension bits ? 16-bit bidirectional barrel shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/once debug programming interface 1.1.2 memory ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low-cost, high-volume flash solution 8k 16 bit words of program flash 1k 16-bit words of program ram 2k 16-bit words of data flash 1k 16-bit words of data ram 2k 16-bit words of boot flash ? programmable boot flash supports customized boot code and field upgrades of stored code through a variety of interfaces (jtag) 1.1.3 peripheral circuits for dsp56f802 ? pulse width modulator (pwm) with six pwm outputs with deadtime insertion and fault protection; supports both center- and edge-aligned modes ? two 12-bit, analog-to-digital converters (adcs), 1 x 2 channel and 1 x 3 channel, which support two simultaneous conversions; adc and pwm modules can be synchronized ? two general purpose quad timers with two external pins (or two gpio) ? serial communication interface (sci) with two pins (or two gpio) ? four multiplexed general purpose i/o (gpio) pins
dsp56f802 description motorola dsp56f802 preliminary technical data 3 ? computer-operating properly (cop) watchdog timer ? external interrupts via gpio ? trimmable on-chip relaxation oscillator ? external reset pin for hardware reset ? jtag/on-chip emulation (once?) for unobtrusive, processor speed-independent debugging ? software-programmable, phase lock loop-based frequency synthesizer for the dsp core clock 1.1.4 energy information ? fabricated in high-density cmos with 5v tolerant, ttl-compatible digital inputs ? uses a single 3.3v power supply ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available ? integrated power supervisor 1.2 dsp56f802 description the dsp56f802 is a member of the dsp56800 core-based family of digital signal processors (dsps). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the dsp56f802 is well-suited for many applications. the dsp56f802 includes many peripherals that are especially useful for applications such as motion control, home appliances, encoders, tachometers, limit switches, power supply and control, engine management, and industrial control for power, lighting, automation and hvac. the dsp56800 core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the dsp56f802 supports program execution from either internal or external memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the dsp56f802 also provides and up to 4 general purpose input/output (gpio) lines, depending on peripheral configuration. the dsp56f802 dsp controller includes 8k words (16-bit) of program flash and 2k words of data flash (each programmable through the jtag port) with 1k words of both program and data ram. a total of 2k words of boot flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main program and data flash memory areas. both program and data flash memories can be independently bulk erased or erased in page sizes of 256 words. the boot flash memory can also be either bulk or page erased. a key application-specific feature of the dsp56f802 is the inclusion of a pulse width modulator (pwm) module. this modules incorporates six complementary, individually programmable pwm signal outputs to enhance motor control functionality. complementary operation permits programmable dead-time insertion, and separate top and bottom output polarity control. the up-counter value is programmable to support a continuously variable pwm frequency. both edge and center aligned synchronous pulse width control (0% to 100% modulation) are supported. the device is capable of controlling most motor types: acim (ac
4 dsp56f802 preliminary technical data motorola induction motors), both bdc and bldc (brush and brushless dc motors), srm and vrm (switched and variable reluctance motors), and stepper motors. the pwms incorporate fault protection with sufficient output drive capability to directly drive standard opto-isolators. a smoke-inhibit, write-once protection feature for key parameters is also included. the pwm is double-buffered and includes interrupt control to permit integral reload rates to be programmable from 1 to 16. the pwm modules provide a reference output to synchronize the analog-to-digital converters. the dsp56f802 incorporates two 12-bit analog-to-digital converters (adcs) with a total of five channels. a full set of standard programmable peripherals is provided that include a serial communications interface (sci), and two quad timers. any of these interfaces can be used as general-purpose input/outputs (gpio) if that function is not required. an on-chip relaxation oscillator eliminates the need for an external crystal. 1.3 best in class development environment the sdk (software development kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique c application code independent of component architecture. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards support concurrent engineering. together, the sdk, codewarrior, and evms create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 product documentation the four documents listed in table 1 are required for a complete description and proper design with the dsp56f802. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors/dsp . table 1. dsp56f802 chip documentation topic description order number dsp56800 family manual detailed description of the dsp56800 family architecture, and 16-bit dsp core processor and the instruction set dsp56800fm/d dsp56f801/803/805/807 users manual detailed description of memory, peripherals, and interfaces of the dsp56f801, dsp56f802, dsp56f803, dsp56f805, and dsp56f807 dsp56f801-7um/d dsp56f802 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) dsp56f802/d dsp56f802 product brief summary description and block diagram of the dsp56f802 core, memory, peripherals and interfaces dsp56f802pb/d
data sheet conventions motorola dsp56f802 preliminary technical data 5 1.5 data sheet conventions this data sheet uses the following conventions: overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. asserted a high true (active high) signal is high or a low true (active low) signal is low. deasserted a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for vil, vol, vih, and voh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
6 dsp56f802 preliminary technical data motorola part 2 signal/connection descriptions 2.1 introduction the input and output signals of the dsp56f802 are organized into functional groups, as shown in table 2 and as illustrated in figure 2 . in table 3 through table 11 , each table row describes the signal or signals present on a pin. table 2. functional group pin allocations functional group number of pins detailed description power (v dd or v dda )3 table 3 ground (v ss, v ssa, tcs) 4 table 4 supply capacitors 2 table 5 program control 1 table 6 pulse width modulator (pwm) port and fault input 7 table 7 serial communications interface (sci) port 1 1. alternately, gpio pins 2 table 8 analog-to-digital converter (adc) port (including v ref) 6 table 9 quad timer module port 2 table 10 jtag/on-chip emulation (once) 5 table 11
introduction motorola dsp56f802 preliminary technical data 7 figure 2. dsp56f802 signals identified by functional group 1 1. alternate pin functionality is shown in parenthesis. dsp56f802 power port ground port power port ground port sci0 port or gpio v dd v ss v dda v ssa vcapc tck tms tdi tdo trst jtag/ once ? port pwma0-5 fault a0 txd0 (gpiob0) rxd0 (gpiob1) ana2-4, ana6-7 vref td1-2 (gpioa1-2) reset quad timer d or gpio adca port other supply port 2 3* 1 1 2 1 1 1 1 1 program control 6 1 1 1 5 1 2 1 * includes tcs pin which is reserved for factory use and is tied to vss
8 dsp56f802 preliminary technical data motorola 2.2 power and ground signals 2.3 interrupt and program control signals table 3. power inputs no. of pins signal name signal description 2 v dd power these pins provide power to the internal structures of the chip, and should all be attached to v dd. 1 v dda analog power this pin supplies an analog power source. table 4. grounds no. of pins signal name signal description 2 v ss gnd these pins provide grounding for the internal structures of the chip, and should all be attached to v ss. 1 v ssa analog ground this pin supplies an analog ground. 1 tcs tcs this pin is reserved for factory use and must be tied to v ss for normal use. in block diagrams, this pin is considered an additional v ss. table 5. supply capacitors and vpp no. of pins signal name signal type state during reset signal description 2 vcapc supply supply vcapc - connect each pin to a 2.2 m f bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). for more information, refer to section 5.2 table 6. program control signals no. of pins signal name signal type state during reset signal description 1 reset input input reset this input is a direct hardware reset on the processor. when reset is asserted low, the dsp is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the extboot pin. the internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware dsp reset is required and it is necessary not to reset the once/jtag module. in this case, assert reset , but do not assert trst .
pulse width modulator (pwm) signals motorola dsp56f802 preliminary technical data 9 2.4 pulse width modulator (pwm) signals 2.5 serial communications interface (sci) signals 2.6 analog-to-digital converter (adc) signals table 7. pulse width modulator (pwma) signals no. of pins signal name signal type state during reset signal description 6 pwma0-5 output tri-stated pwma0-5 these are six pwma output pins. 1 faulta0 input input faulta0 this fault input is used for disabling selected pwma outputs in cases where fault conditions originate off chip. table 8. serial communications interface (sci0) signals no. of pins signal name signal type state during reset signal description 1 txd0 gpiob0 output input/ output input input transmit data (txd0) transmit data output port b gpio this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. after reset, the default state is sci output. 1 rxd0 gpiob1 input input/ output input input receive data (rxd0) receive data input port b gpio this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. after reset, the default state is sci input. table 9. analog to digital converter signals no. of pins signal name signal type state during reset signal description 3 ana2-4 input input ana2-4 analog inputs to adc channel 1 2 ana6-7 input input ana6-7 analog inputs to adc channel 2 1 vref input input vref analog reference voltage. must be set to v dda - 0.3v = 3.0v for optimal performance.
10 dsp56f802 preliminary technical data motorola 2.7 quad timer module signals 2.8 jtag/once table 10. quad timer module signals no. of pins signal name signal type state during reset signal description 2 td1-2 gpioa1-2 input/ output input/ output input input td1-2 timer d channel 1-2 port a gpio these pins are general purpose i/o (gpio) pins that can individually be programmed as input or output pins. after reset, the default state is the quad timer input. table 11. jtag/on-chip emulation (once) signals no. of pins signal name signal type state during reset signal description 1 tck input input, pulled low internally test clock input this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/once port. the pin is connected internally to a pull-down resistor. 1 tms input input, pulled high internally test mode select input this input pin is used to sequence the jtag tap controllers state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdi input input, pulled high internally test data input this input pin provides a serial input data stream to the jtag/once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdo output tri-stated test data output this tri-statable output pin provides a serial output data stream from the jtag/once port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. 1 trst input input, pulled high internally test reset as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment, since the once/jtag module is under the control of the debugger. in this case it is not necessary to assert trst when asserting reset . outside of a debugging environment reset should be permanently asserted by grounding the signal, thus disabling the once/jtag module on the dsp.
general characteristics motorola dsp56f802 preliminary technical data 11 part 3 specifications 3.1 general characteristics the dsp56f802 is fabricated in high-density cmos with 5-volt tolerant ttl-compatible digital inputs. the term 5-volt tolerant refers to the capability of an i/o pin, built on a 3.3v compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels without being damaged. absolute maximum ratings given in table 12 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the dsp56f802 dc and ac electrical specifications are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterization and device qualifications have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 12. absolute maximum ratings characteristic symbol min max unit supply voltage v dd v ss C 0.3 v ss + 4.0 v all other input voltages, excluding analog inputs v in v ss C 0.3 v ss + 5.5v v analog inputs anax, v ref v in v ss C 0.3 v dda + 0.3v v current drain per pin excluding v dd , v ss , & pwm ouputs i 10 ma current drain per pin for pwm outputs i 20 ma junction temperature t j 150c storage temperature range t stg -55 150 c
12 dsp56f802 preliminary technical data motorola 3.2 dc electrical characteristics table 13. recommended operating conditions characteristic symbol min max unit supply voltage v dd 3.0 3.6 v ambient operating temperature t a -40 85 c table 14. thermal characteristics 1 1. see section 5.1 for more detail. characteristic 32-pin lqfp symbol value unit junction-to-ambient (estimated) r q ja 53.2 c/w i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd x v dd ) + p i/o w maximum allowed p d p dmax (t j - t a ) / q ja c table 15. dc electrical characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min typ max unit input high voltage v ih 2.0 5.5 v input low voltage v il -0.3 0.8 v input current low (pullups/pulldowns disabled) i il -1 1 m a input current high (pullups/pulldowns disabled) i ih -1 1 m a typical pullup or pulldown resistance r pu , r pd 30k w input/output tri-state current low i ozl -10 10 m a input/output tri-state current low i ozh -10 10 m a output high voltage (at ioh) v oh v dd C 0.7 v output low voltage (at iol) v ol 0.4v output high current i oh -4ma output low current i ol 4ma input capacitance c in 8pf output capacitance c out 12pf
dc electrical characteristics motorola dsp56f802 preliminary technical data 13 figure 3. maximum run idd vs. frequency (see note 4 above) pwm pin output source current 1 i ohp -10 ma pwm pin output sink current 2 i olp 16ma v dd supply current i ddt 3 run 4 103 138 ma wait 5 7298ma stop 60 84 ma low voltage interrupt 6 core voltage interrupt v ei 2.4 2.7 2.2 2.9 v power on reset 7 por 1.7 2.0 v 1. pwm pin output source current measured with 50% duty cycle. 2. pwm pin output sink current measured with 50% duty cycle. 3. i ddt = i dd + i dda (total supply current for vdd + vdda) 4. run (operating) i dd measured using 8mhz clock source. all inputs 0.2v from rail; outputs unloaded. all ports configured as inputs; measured with all modules enabled. 5. wait i dd measured using internal relaxation oscillator set to 8 mhz; all inputs 0.2v from rail; no dc loads; less than 50 pf on all outputs. c l = 20 pf on extal; all ports configured as inputs; measured with pll enabled. 6. low voltage interrupt monitors the v dd supply. when v dd drops below v ei value, an interrupt is generated. functionality of the device is guaranteed under transient conditions when v dda > v ei . 7. power-on reset occurs whenever the internally regulated 2.5v digital supply drops below v por . while power is ramping up, this signal remains active for as long as the internal 2.5v supply is below 1.5v no matter how long the ramp up rate is. the internally regulated voltage is typically 100 mv less than v dd during ramp up until 2.5v is reached, at which time it self regulates. table 15. dc electrical characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min typ max unit 180 150 120 90 60 30 0 idd (ma) digital (vdd=3.6v) analog (vdda=3.6v) total freq. (mhz) 0 40 60 80 20 idd (ma) 40 180 150 120 90 60 30 0
14 dsp56f802 preliminary technical data motorola 3.3 ac electrical characteristics timing waveforms in section 3.3 are tested with a v il maximum of 0.8 v and a v ih minimum of 2.0 v for all pins except xtal, which is tested using the input levels in section 3.2 in figure 4 the levels of v ih and v il for an input signal are shown. figure 4. input signal measurement references figure 5 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state. ? tri-stated, when a bus or signal is placed in a high impedance state. ? data valid state, when a signal level has reached v ol or v oh. ? data invalid state, when a signal level is in transition between v ol and v oh. figure 5. signal states v ih v il fall time input signal note: the midpoint is v il + (v ih C v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
flash memory characteristics motorola dsp56f802 preliminary technical data 15 3.4 flash memory characteristics table 16. flash memory truth table mode xe 1 1. x address enable, all rows are disabled when xe = 0 ye 2 2. y address enable, ymux is disabled when ye = 0 se 3 3. sense amplifier enable oe 4 4. output enable, tri-state flash data out bus when oe = 0 prog 5 5. defines program cycle erase 6 6. defines erase cycle mas1 7 7. defines mass erase cycle, erase whole block nvstr 8 8. defines non-volatile store cycle standby l l l l l l l l read h h h h l l l l word program h h l l h l l h page erase h l l l l h l h mass erase h l l l l h h h table 17. ifren truth table mode ifren = 1 ifren = 0 read read information block read main memory block word program program information block program main memory block page erase erase information block erase main memory block mass erase erase both blocks erase main memory block
16 dsp56f802 preliminary technical data motorola table 18. timing symbols characteristic symbol see figure(s) prog/erase to nvstr set up time t nvs figure 6 , figure 7 , figure 8 nvstr hold time t nvh figure 6 , figure 7 nvstr hold time(mass erase) t nvh1 figure 8 nvstr to program set up time t pgs figure 6 program hold time t pgh figure 6 address/data set up time t ads figure 6 address/data hold time t adh figure 6 recovery time t rcv figure 6 , figure 7 , figure 8 cumulative program hv period t hv figure 6 program time t prog figure 6 erase time t erase figure 7 mass erase time t me figure 8 table 19. flash timing parameters operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf characteristic symbol min typ max unit program time t prog 20 us erase time t erase 20 ms mass erase time t me 100 ms endurance 1 1. one cycle is equal to an erase, program, and read. e cyc 10,000 20,000 cycles data retention @ 5,000 cycles 1 d ret 10 30 years the following parameters should only be used in the manual word programming mode. prog/erase to nvstr set up time t nvs 5 us nvstr hold time t nvh 5 us nvstr hold time(mass erase) t nvh1 100 us nvstr to program set up time t pgs 10us recovery time t rcv 1 us
flash memory characteristics motorola dsp56f802 preliminary technical data 17 figure 6. flash program cycle figure 7. flash erase cycle xadr yadr ye din prog nvstr tnvs tpgs tadh tprog tads tpgh tnvh trcv thv ifren xe xadr ye=se=oe=mas1=0 erase nvstr tnvs tnvh trcv terase ifren xe
18 dsp56f802 preliminary technical data motorola figure 8. flash mass erase cycle 3.5 clock operation the dsp56f802 device clock is derived from an on-chip relaxation oscillator. the internal pll generates a master reference frequency that determines the speed at which chip operations occur. the precs bit in the pllcr (phase-locked loop control register) word (bit 2) must be set to 0 for internal oscillator use. 3.5.1 use of on-chip relaxation oscillator the dsp56f802 internal relaxation oscillator provides the chip clock without the need for an external crystal or ceramic resonator. the frequency output of this internal oscillator can be corrected by adjusting the 8-bit iosctl (internal oscillator control) register. each bit added or deleted changes the output frequency of the oscillator allowing incremental adjustment until the desired frequency is achieved. figures 9 and 10 show the typical characteristics of the dsp56f802 relaxation oscillator with respect to temperature and trim value. during factory production test, an oscillator calibration procedure is executed which determines an optimum trim value for a given device (8 mhz at 25 o c). this optimum trim value is then stored at address $103f in the data flash information block and recalled during a trim routine in the boot sequence (executed after power-up and reset). this trim routine automatically sets the oscillator frequency by programming the iosctl register with the optimum trim value. due to the inherent frequency tolerances required for sci communication, changing the factory-trimmed oscillator frequency is not recommended. if modification of the boot flash contents are required, code must be included which retrieves the optimum trim value (from address $103f in the data flash information block) and writes it to the iosctl register. note that the ifren bit in the data flash control register must be set in order to read the data flash information block. xadr ye=se=oe=0 erase nvstr tnvs tnvh1 trcv tme mas1 ifren xe
clock operation motorola dsp56f802 preliminary technical data 19 figure 9. typical relaxation oscillator frequency vs. temperature (trimmed to 8 mhz @ 25 o c) table 20. relaxation oscillator characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c characteristic symbol min typ max unit frequency accuracy 1 1. over full temperature range. d f + 2+ 5% frequency drift over temp d f/ d t+ 0.1 %/ o c frequency drift over supply d f/ d v 0.1 %/v 8.2 8.0 8.3 8.4 7.9 8.1 7.8 75 55 -40 35 -25 15 -5 85 temperature ( o c) output frequency
20 dsp56f802 preliminary technical data motorola figure 10. typical relaxation oscillator frequency vs. trim value @ 25 o c 3.6 reset, stop, wait, mode select, and interrupt timing table 21. reset, stop, wait, mode select, and interrupt timing 1, 5 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf 1. in the formulas, t = clock cycle. for an operating frequency of 80 mhz, t = 12.5 ns. characteristic symbol typical min typical max unit reset assertion to address, data and control signals high impedance t raz 21ns minimum reset assertion duration 2 omr bit 6 = 0 omr bit 6 = 1 2. circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: ? after power-on reset ? when recovering from stop state t ra 275,000t 128t ns ns reset de-assertion to first external address output t rda 33t 34t ns edge-sensitive interrupt request width t irw 1.5t ns 0 102030405060708090a0b0c0d0e0f0 5 6 7 8 9 10 11
quad timer timing motorola dsp56f802 preliminary technical data 21 figure 11. external level-sensitive interrupt timing 3.7 quad timer timing table 22. timer timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz 1. in the formulas listed, t = clock cycle. for 80 mhz operation, t = 12.5 ns. 2. parameters listed are guaranteed by design. characteristic symbol typical min typical max unit timer input period p in 4t+6 ns timer input high/low period p inhl 2t+3 ns timer output period p out 2t ns timer output high/low period p outhl 1t ns figure 12. timer timing general purpose i/o pin irqa b) general purpose i/o t ig timer inputs timer outputs p outhl p outhl p out p in p inhl p inhl
22 dsp56f802 preliminary technical data motorola 3.8 serial communication interface (sci) timing figure 13. rxd pulse width figure 14. txd pulse width 3.9 analog-to-digital converter (adc) characteristics table 23. sci timing operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br (f max *2.5)/(80) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns table 24. adc characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, v ref = v dd -0.3v, adcdiv = 4, 9, or 14, adc clock = 4mhz, 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min typ max unit input voltages v adin 0 v dda 1 v resolution r es 12 12 bits integral non-linearity 2 inl +/- 4 +/- 5 lsb 3 differential non-linearity dnl +/- 0.9 +/- 1 lsb 3 monotonicity guaranteed adc internal clock f adic 0.5 5 mhz conversion range r ad v ssa v dda v rxd sci receive data pin (input) rxd pw txd sci receive data pin (input) txd pw
analog-to-digital converter (adc) characteristics motorola dsp56f802 preliminary technical data 23 figure 15. equivalent analog input circuit 1. parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing. 2.04pf 3. equivalent resistance for the esd isolation resistor and the channel select mux. 500 ohms sampling capacitor at the sample and hold circuit. capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. 1pf power-up time t adpu 2.5 msec conversion time t adc 6 t aic cycles 4 sample time t ads 1 t aic cycles 4 input capacitance c adi 5 pf 4 gain error (transfer gain) e gain 1.00 1.10 1.15 offset voltage v offset +10 +230 +325 mv total harmonic distortion thd 55 60 db signal-to-noise plus distortion sinad 54 56 effective number of bits enob 8.5 9.5 bit spurious free dynamic range sfdr 60 65 db spurious free dynamic range sfdr 65 70 db adc quiescent current (both adcs) i adc 39.3 ma v ref quiescent current (both adcs) i vref 11.85 14.5 ma 1. v dda should be tied to the same potential as v dd via separate traces. v ref must be equal to or less than v dd and must be greater than or equal to 2.7v. 2. measured in 10-90% range. 3. lsb = least significant bit. 4. t aic = 1/ f adic table 24. adc characteristics (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, v ref = v dd -0.3v, adcdiv = 4, 9, or 14, adc clock = 4mhz, 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz characteristic symbol min typ max unit 1 2 3 4 adc analog input
24 dsp56f802 preliminary technical data motorola 3.10 jtag timing table 25. jtag timing 1, 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0C3.6 v, t a = C40 to +85 c, c l 50 pf, f op = 80 mhz 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 80 mhz operation, t = 12.5 ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/8 the processor rate. 3. parameters listed are guaranteed by design. f op dc 10 mhz tck cycle time t cy 100 ns tck clock pulse width t pw 50 ns tms, tdi data setup time t ds 0.4 ns tms, tdi data hold time t dh 1.2 ns tck low to tdo data valid t dv 26.6 ns tck low to tdo tri-state t ts 23.5 ns trst assertion time t trst 50 ns figure 16. test clock input timing diagram tck (input) v m v il v m = v il + (v ih C v il )/2 v m v ih t pw t pw t cy
jtag timing motorola dsp56f802 preliminary technical data 25 figure 17. test access port timing diagram figure 18. trst timing diagram input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t dv t ts t ds t dh trst (input) t trst
26 dsp56f802 preliminary technical data motorola part 4 packaging 4.1 package and pin-out information dsp56f802 this section contains package and pin-out information for the 32-pin lqfp configuration of the dsp56f802. figure 19. top view, dsp56f802 32-pin lqfp package pin 1 orientation mark pwma4 pwma5 td1 td2 txdo vss vdd rxd0 tcs tck tms tdi vcapc2 tdo trst reset ana3 vref ana2 faulta0 vss vdd vssa vdda pwma3 pwma2 pwma1 vcapc1 pwma0 ana7 ana6 ana4 9 25 17 motorola dsp56f802
package and pin-out information dsp56f802 motorola dsp56f802 preliminary technical data 27 table 26. dsp56f802 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1pwma49 tcs 17 v dda 25 ana4 2pwma510 tck 18 v ssa 26 ana6 3td111tms19v dd 27 ana7 4td212tdi20v ss 28 pwma0 5 txdo 13 vcapc2 21 faulta0 29 vcapc1 6v ss 14 tdo 22ana230pwma1 7v dd 15 trst 23 vref 31 pwma2 8 rxd0 16 reset 24 ana3 32 pwma3
28 dsp56f802 preliminary technical data motorola figure 20. 32-pin lqfp mechanical information (case 873a) notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane a, b and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimensions b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more then 0.08 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protursion: 0.07 mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead dim a min max millimeters a1 a2 b b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 7.00 bsc e e e1 l1 1.00 ref o 07 o1 12 l 0.70 r1 0.08 0.20 r2 1.40 1.60 0.05 1.45 0.15 1.35 0.45 0.30 9.00 bsc s 0.20 ref 0.80 bsc 9.00 bsc 7.00 bsc 0.50 ref 0.08 --
thermal design considerations motorola dsp56f802 preliminary technical data 29 part 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature c r q ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r q ja = package junction-to-ambient thermal resistance c/w r q jc = package junction-to-case thermal resistance c/w r q ca = package case-to-ambient thermal resistance c/w r q jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r q ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb), or otherwise change the thermal dissipation capability of the area surrounding the device on the pcb. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r q ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. definitions: a complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: ? measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. ? measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junction to board thermal resistance. ? use the value obtained by the equation (t j C t t )/p d where t t is the temperature of the package case determined by a thermocouple. t j t a p d r q ja () + = r q ja r q jc r q ca + =
30 dsp56f802 preliminary technical data motorola the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition on page 45. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. hence, the new thermal metric, thermal characterization parameter, or y jt , has been defined to be (t j C t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 5.2 electrical design considerations use the following list of considerations to assure correct dsp operation: ? provide a low-impedance path from the board power supply to each v dd pin on the dsp, and from the board ground to each v ss (gnd) pin. ? the minimum bypass requirement is to place six 0.01C0.1 m f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the ten v dd /v ss pairs, including v dda /v ssa. the vcap capacitors must be 150 milliohm or less esr capacitors. ? ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead. ? use at least a four-layer printed circuit board (pcb) with two inner layers for v dd and v ss . ? bypass the v dd and v ss layers of the pcb with approximately 100 m f, preferably with a high- grade capacitor such as a tantalum capacitor. ? because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and gnd circuits. ? take special care to minimize noise levels on the vref, v dda and v ssa pins. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
electrical design considerations motorola dsp56f802 preliminary technical data 31 ? designs that utilize the trst pin for jtag port or once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer products, should tie these pins together. trst must be asserted at power up for proper operation. ? because the flash memory is programmed through the jtag/once port, designers should provide an interface to this port to allow in-circuit flash programming. part 6 ordering information table 27 lists the pertinent information needed to place an order. consult a motorola semiconductor sales office or authorized distributor to determine availability and to order parts. table 27. dsp56f802 ordering information part supply voltage package type pin count frequency (mhz) order number dsp56f802 3.0C3.6 v low profile plastic quad flat pack (lqfp) 32 80 dsp56f802ta80
dsp56f802/d motorola and the stylized m logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. ? motorola, inc. 2002. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1C303C675C2140 or 1C800C441C2447 japan: motorola japan ltd.; sps, technical information center, 3C20C1, minamiCazabu. minatoCku, tokyo 106C8573 japan. 81C3C3440C3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kon g . 852C26668334 technical information center: 1C800C521C6274 home page: http://www.motorola.com/semiconductors/ motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application o r use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical param eters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all oper ating parameters, including typicals must be validated for each customer application by customers technical experts. motorola does not convey any licens e under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for sur gical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer s hall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.

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